Shortening a design time period of a semiconductor integrated circuit currently becomes difficult as a circuit scale increases, process technologies are miniaturized, and an operating frequency of circuit becomes high. A layout design of the semiconductor integrated circuit is to be performed efficiently under these circumstances. To this end, the layout design is performed with the integrated circuit split, and timing modifications subsequent to the placing cells in the semiconductor integrated circuit and wiring wire lines connecting terminals of the placed cells are made through an engineering change order (ECO) process. Through the ECO process, the timing modification is performed by modifying logic of the circuit to reduce path delay, or modifying the layout of a circuit element. A technique of adjusting a clock delay is also used.
Related art is described in Japanese Laid-Open Patent Publication No. 2002-149730, and Japanese Laid-Open Patent Publication No. 2002-245109.
The ECO process described with reference to related art provides a remedial method to correct a timing error. For example, the ECO process makes a change to a circuit element (cell) having a different delay value and a different load driving power but having the same logic. Also through the ECO process, a repeater cell or a delay buffer is inserted, and a skew adjustment of a clock path is performed. The timing adjustment may be performed by changing a mounting position of a cell. These timing modification methods are performed by adjusting a delay through cell changing. The timing modification methods modify a large delay value and are thus considered effective in a timing verification typically performed during a middle design phase, in which a relatively large error still remains.
The modification through cell changing greatly changes the delay value at a modification location, possibly causing a new timing error. Even if a location degrading timing slightly is present in the timing correction during the middle design phase, such a location typically goes unnoticed because of the presence of another large error. As the final design phase draws, a new error may be caused during the timing correction, and affect the design process.
If a hold-time error is caused, a delay buffer may be inserted into a data path to delay a signal propagating through the data path. Depending on the delay value and the insertion location of the delay buffer, a setup error may be caused in another path routing through the inserted delay buffer. If a new timing error is caused in the timing correction close to the deadline of the design process, the design schedule may be delayed.
A hold-time error of a small value may still remain during the final design phase. The correction of the hold-time error only is desirable, and no adverse effect is desirable from the correction of the timing of the hold-time error.